638 lines
25 KiB
C++
638 lines
25 KiB
C++
// This file is part of OpenCV project.
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// It is subject to the license terms in the LICENSE file found in the top-level directory
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// of this distribution and at http://opencv.org/license.html.
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#ifndef OPENCV_DNN_CUDA4DNN_CSL_CUDNN_CONVOLUTION_HPP
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#define OPENCV_DNN_CUDA4DNN_CSL_CUDNN_CONVOLUTION_HPP
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#include "cudnn.hpp"
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#include "activation.hpp"
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#include "../pointer.hpp"
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#include "../workspace.hpp"
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#include <cudnn.h>
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#include <cstddef>
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#include <array>
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#include <algorithm>
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#include <vector>
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#include <type_traits>
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#include <iterator>
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namespace cv { namespace dnn { namespace cuda4dnn { namespace csl { namespace cudnn {
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/** describe convolution filters
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*
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* @tparam T type of elements in the kernels
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*/
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template <class T>
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class FilterDescriptor {
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public:
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FilterDescriptor() noexcept : descriptor{ nullptr } { }
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FilterDescriptor(const FilterDescriptor&) = delete;
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FilterDescriptor(FilterDescriptor&& other) noexcept
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: descriptor{ other.descriptor } {
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other.descriptor = nullptr;
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}
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/** constructs a filter descriptor from the filter dimensions provided in \p shape
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*
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* Shape dimensions:
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* 0: number of filters
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* 1: number of input feature maps
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* 2..n: kernel dimensions
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*
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* Exception Guarantee: Strong
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*/
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template <class SequenceContainer, typename = decltype(std::begin(std::declval<SequenceContainer>()))>
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FilterDescriptor(const SequenceContainer& shape) {
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constructor(shape.begin(), shape.end());
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}
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/** constructs a filter descriptor from the filter dimensions provided in [begin, end)
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*
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* Shape dimensions:
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* 0: number of filters
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* 1: number of input feature maps
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* 2..n: kernel dimensions
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*
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* Exception Guarantee: Strong
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*/
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template <class ForwardItr, typename = typename std::enable_if<!std::is_integral<ForwardItr>::value, void>::type> // TODO is_iterator
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FilterDescriptor(ForwardItr begin, ForwardItr end) {
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constructor(begin, end);
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}
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/** constructs a filter descriptor from the filter dimensions provided as arguments
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*
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* Shape dimensions:
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* 0: number of filters
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* 1: number of input feature maps
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* 2..n: kernel dimensions
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*
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* Exception Guarantee: Strong
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*/
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template <class ...Sizes>
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FilterDescriptor(Sizes ...sizes) {
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static_assert(sizeof...(Sizes) >= 3, "filter descriptors must have at least three dimensions");
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static_assert(sizeof...(Sizes) <= CUDNN_DIM_MAX, "required rank exceeds maximum supported rank");
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std::array<int, sizeof...(Sizes)> dims = { static_cast<int>(sizes)... };
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constructor(std::begin(dims), std::end(dims));
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}
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~FilterDescriptor() noexcept {
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if (descriptor != nullptr) {
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/* cudnnDestroyFilterDescriptor will not fail for a valid descriptor object */
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CUDA4DNN_CHECK_CUDNN(cudnnDestroyFilterDescriptor(descriptor));
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}
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}
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FilterDescriptor& operator=(const FilterDescriptor&) = delete;
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FilterDescriptor& operator=(FilterDescriptor&& other) noexcept {
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descriptor = other.descriptor;
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other.descriptor = nullptr;
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return *this;
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};
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cudnnFilterDescriptor_t get() const noexcept { return descriptor; }
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private:
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template <class ForwardItr>
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void constructor(ForwardItr start, ForwardItr end) {
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CV_Assert(start != end);
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CV_Assert(std::distance(start, end) >= 3);
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CV_Assert(std::distance(start, end) <= CUDNN_DIM_MAX);
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CUDA4DNN_CHECK_CUDNN(cudnnCreateFilterDescriptor(&descriptor));
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try {
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const auto rank = std::distance(start, end);
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if (rank == 4) {
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std::array<int, 4> dims;
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std::copy(start, end, std::begin(dims));
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CUDA4DNN_CHECK_CUDNN(
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cudnnSetFilter4dDescriptor(
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descriptor,
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detail::get_data_type<T>(), CUDNN_TENSOR_NCHW,
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dims[0], dims[1], dims[2], dims[3]
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)
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);
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} else {
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std::vector<int> dims(start, end);
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CUDA4DNN_CHECK_CUDNN(
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cudnnSetFilterNdDescriptor(
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descriptor,
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detail::get_data_type<T>(), CUDNN_TENSOR_NCHW,
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dims.size(), dims.data()
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)
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);
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}
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} catch (...) {
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/* cudnnDestroyFilterDescriptor will not fail for a valid descriptor object */
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CUDA4DNN_CHECK_CUDNN(cudnnDestroyFilterDescriptor(descriptor));
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throw;
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}
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}
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cudnnFilterDescriptor_t descriptor;
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};
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/** describes a convolution operation
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*
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* @tparam T type of element participating in convolution
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*/
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template <class T>
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class ConvolutionDescriptor {
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public:
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ConvolutionDescriptor() noexcept : descriptor{ nullptr } { }
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ConvolutionDescriptor(const ConvolutionDescriptor&) = delete;
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ConvolutionDescriptor(ConvolutionDescriptor&& other) noexcept
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: descriptor{ other.descriptor } {
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other.descriptor = nullptr;
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}
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/** constructs a convolution descriptor
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*
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* Pre-conditions:
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* - \p zero_padding, \p stride and \p dilation must have the same size
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*
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* The length of the containers is interpreted as the order of the convolution.
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*
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* Exception Guarantee: Strong
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*/
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template <class SequenceContainer, typename = decltype(std::begin(std::declval<SequenceContainer>()))>
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ConvolutionDescriptor(
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const SequenceContainer& zero_padding,
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const SequenceContainer& stride,
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const SequenceContainer& dilation,
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std::size_t group_count)
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{
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constructor(zero_padding, stride, dilation, group_count);
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}
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~ConvolutionDescriptor() noexcept {
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if (descriptor != nullptr) {
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/* cudnnDestroyConvolutionDescriptor will not fail for a valid descriptor object */
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CUDA4DNN_CHECK_CUDNN(cudnnDestroyConvolutionDescriptor(descriptor));
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}
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}
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ConvolutionDescriptor& operator=(const ConvolutionDescriptor&) = delete;
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ConvolutionDescriptor& operator=(ConvolutionDescriptor&& other) noexcept {
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descriptor = other.descriptor;
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other.descriptor = nullptr;
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return *this;
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};
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cudnnConvolutionDescriptor_t get() const noexcept { return descriptor; }
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private:
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template <class SequenceContainer>
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void constructor(
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const SequenceContainer& zero_padding,
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const SequenceContainer& stride,
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const SequenceContainer& dilation,
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std::size_t group_count)
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{
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CV_Assert(zero_padding.size() == stride.size());
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CV_Assert(zero_padding.size() == dilation.size());
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CUDA4DNN_CHECK_CUDNN(cudnnCreateConvolutionDescriptor(&descriptor));
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try {
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const auto rank = zero_padding.size();
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if (rank == 2) {
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CUDA4DNN_CHECK_CUDNN(
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cudnnSetConvolution2dDescriptor(
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descriptor,
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zero_padding[0], zero_padding[1],
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stride[0], stride[1],
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dilation[0], dilation[1],
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CUDNN_CROSS_CORRELATION,
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detail::get_data_type<T>()
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)
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);
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} else {
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std::vector<int> ipadding(std::begin(zero_padding), std::end(zero_padding));
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std::vector<int> istride(std::begin(stride), std::end(stride));
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std::vector<int> idilation(std::begin(dilation), std::end(dilation));
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CUDA4DNN_CHECK_CUDNN(
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cudnnSetConvolutionNdDescriptor(
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descriptor,
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rank, ipadding.data(), istride.data(), idilation.data(),
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CUDNN_CROSS_CORRELATION,
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detail::get_data_type<T>()
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)
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);
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}
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CUDA4DNN_CHECK_CUDNN(cudnnSetConvolutionGroupCount(descriptor, group_count));
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#if CUDNN_MAJOR >= 8
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/* cuDNN 7 and below use FMA math by default. cuDNN 8 includes TF32 Tensor Ops
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* in the default setting. TF32 convolutions have lower precision than FP32.
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* Hence, we set the math type to CUDNN_FMA_MATH to reproduce old behavior.
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*/
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CUDA4DNN_CHECK_CUDNN(cudnnSetConvolutionMathType(descriptor, CUDNN_FMA_MATH));
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#endif
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if (std::is_same<T, half>::value)
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CUDA4DNN_CHECK_CUDNN(cudnnSetConvolutionMathType(descriptor, CUDNN_TENSOR_OP_MATH));
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} catch (...) {
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/* cudnnDestroyConvolutionDescriptor will not fail for a valid descriptor object */
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CUDA4DNN_CHECK_CUDNN(cudnnDestroyConvolutionDescriptor(descriptor));
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throw;
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}
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}
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cudnnConvolutionDescriptor_t descriptor;
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};
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/** wrapper around a convolution algorithm
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*
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* @tparam T type of elements being convolved
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*/
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template <class T>
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class ConvolutionAlgorithm {
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public:
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ConvolutionAlgorithm() noexcept : workspace_size{ 0 } { }
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ConvolutionAlgorithm(ConvolutionAlgorithm&) = default;
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ConvolutionAlgorithm(ConvolutionAlgorithm&&) = default;
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/** selects a good algorithm for convolution for given configuration
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*
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* Exception Guarantee: Strong
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*/
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ConvolutionAlgorithm(
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const Handle& handle,
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const ConvolutionDescriptor<T>& convDesc,
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const FilterDescriptor<T>& filterDesc,
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const TensorDescriptor<T>& inputDesc,
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const TensorDescriptor<T>& outputDesc)
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{
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#if CUDNN_MAJOR >= 8
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int requestedAlgoCount = 0, returnedAlgoCount = 0;
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CUDA4DNN_CHECK_CUDNN(cudnnGetConvolutionForwardAlgorithmMaxCount(handle.get(), &requestedAlgoCount));
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std::vector<cudnnConvolutionFwdAlgoPerf_t> results(requestedAlgoCount);
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CUDA4DNN_CHECK_CUDNN(
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cudnnGetConvolutionForwardAlgorithm_v7(
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handle.get(),
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inputDesc.get(), filterDesc.get(), convDesc.get(), outputDesc.get(),
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requestedAlgoCount,
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&returnedAlgoCount,
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&results[0]
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)
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);
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size_t free_memory, total_memory;
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CUDA4DNN_CHECK_CUDA(cudaMemGetInfo(&free_memory, &total_memory));
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bool found_conv_algorithm = false;
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for (int i = 0; i < returnedAlgoCount; i++)
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{
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if (results[i].status == CUDNN_STATUS_SUCCESS &&
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results[i].algo != CUDNN_CONVOLUTION_FWD_ALGO_WINOGRAD_NONFUSED &&
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results[i].memory < free_memory)
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{
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found_conv_algorithm = true;
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algo = results[i].algo;
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workspace_size = results[i].memory;
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break;
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}
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}
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if (!found_conv_algorithm)
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CV_Error (cv::Error::GpuApiCallError, "cuDNN did not return a suitable algorithm for convolution.");
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#else
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CUDA4DNN_CHECK_CUDNN(
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cudnnGetConvolutionForwardAlgorithm(
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handle.get(),
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inputDesc.get(), filterDesc.get(), convDesc.get(), outputDesc.get(),
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CUDNN_CONVOLUTION_FWD_PREFER_FASTEST,
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0, /* no memory limit */
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&algo
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)
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);
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CUDA4DNN_CHECK_CUDNN(
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cudnnGetConvolutionForwardWorkspaceSize(
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handle.get(),
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inputDesc.get(), filterDesc.get(), convDesc.get(), outputDesc.get(),
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algo, &workspace_size
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)
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);
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#endif
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}
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ConvolutionAlgorithm& operator=(const ConvolutionAlgorithm&) = default;
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ConvolutionAlgorithm& operator=(ConvolutionAlgorithm&& other) = default;
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cudnnConvolutionFwdAlgo_t get() const noexcept { return algo; }
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/** number of bytes of workspace memory required by the algorithm */
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std::size_t get_workspace_size() const noexcept { return workspace_size; }
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private:
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cudnnConvolutionFwdAlgo_t algo;
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std::size_t workspace_size;
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};
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/** gives the shape of the output tensor of convolution
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*
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* Exception Guarantee: Basic
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*/
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template <class T>
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void getConvolutionForwardOutputDim(
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const ConvolutionDescriptor<T>& convDesc,
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const FilterDescriptor<T>& filterDesc,
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const TensorDescriptor<T>& inputDesc,
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std::vector<int>& output)
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{
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output.clear();
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output.resize(CUDNN_DIM_MAX); /* we use `output` to hold temporaries */
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std::vector<int> temp(CUDNN_DIM_MAX);
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cudnnDataType_t tempDataType;
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CUDA4DNN_CHECK_CUDNN(
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cudnnGetTensorNdDescriptor(
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inputDesc.get(),
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CUDNN_DIM_MAX + 1, /* according to docs, this is what we do to get the rank */
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&tempDataType,
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output.data(),
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temp.data(),
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temp.data()
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)
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);
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const auto rank = output[0];
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output.resize(rank);
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CUDA4DNN_CHECK_CUDNN(
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cudnnGetConvolutionNdForwardOutputDim(
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convDesc.get(), inputDesc.get(), filterDesc.get(), rank, output.data()
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)
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);
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}
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/** @brief performs convolution
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*
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* dstValue = alpha * result + beta * priorDstValue
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*
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* @tparam T convolution element type (must be `half` or `float`)
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*
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* @param handle valid cuDNN Handle
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* @param convDesc convolution description
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* @param convAlgo algorithm to use for convolution
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* @param workspace workspace memory which meets the requirements of \p convAlgo
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* @param filterDesc filter descriptor
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* @param[in] filterPtr pointer to device memory containing the filters
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* @param inputDesc tensor descriptor describing the input
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* @param[in] inputPtr pointer to input tensor in device memory
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* @param alpha result scale factor
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* @param beta previous value scale factor
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* @param outputDesc tensor descriptor describing the output
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* @param[out] outputPtr pointer to output tensor in device memory
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*
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* Exception Guarantee: Basic
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*/
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template <class T>
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void convolve(
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const Handle& handle,
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const ConvolutionDescriptor<T>& convDesc,
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const ConvolutionAlgorithm<T>& convAlgo,
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WorkspaceInstance workspace,
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const FilterDescriptor<T>& filterDesc,
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DevicePtr<const T> filterPtr,
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const TensorDescriptor<T>& inputDesc,
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DevicePtr<const T> inputPtr,
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T alpha, T beta,
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const TensorDescriptor<T>& outputDesc,
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DevicePtr<T> outputPtr)
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{
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CV_Assert(handle);
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CUDA4DNN_CHECK_CUDNN(
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cudnnConvolutionForward(
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handle.get(),
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&alpha, inputDesc.get(), inputPtr.get(),
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filterDesc.get(), filterPtr.get(),
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convDesc.get(), convAlgo.get(),
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static_cast<void*>(workspace.get()), workspace.size_in_bytes(),
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&beta, outputDesc.get(), outputPtr.get()
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)
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);
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}
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template <> inline
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void convolve(
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const Handle& handle,
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const ConvolutionDescriptor<half>& convDesc,
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const ConvolutionAlgorithm<half>& convAlgo,
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WorkspaceInstance workspace,
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const FilterDescriptor<half>& filterDesc,
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DevicePtr<const half> filterPtr,
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const TensorDescriptor<half>& inputDesc,
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DevicePtr<const half> inputPtr,
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half alpha, half beta,
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const TensorDescriptor<half>& outputDesc,
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DevicePtr<half> outputPtr)
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{
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CV_Assert(handle);
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/* we specalize for fp16 as the scaling factors must be provided as `float` */
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float alpha_ = alpha, beta_ = beta;
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CUDA4DNN_CHECK_CUDNN(
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cudnnConvolutionForward(
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handle.get(),
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&alpha_, inputDesc.get(), inputPtr.get(),
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filterDesc.get(), filterPtr.get(),
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convDesc.get(), convAlgo.get(),
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static_cast<void*>(workspace.get()), workspace.size_in_bytes(),
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&beta_, outputDesc.get(), outputPtr.get()
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)
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);
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}
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/** @brief performs convolution, bias addition and activation simultaneously
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*
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* dstValue = act(alpha * conv(input) + bias)
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*
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* @tparam T convolution element type (must be `half` or `float`)
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*
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* @param handle valid cuDNN Handle
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* @param convDesc convolution description
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* @param convAlgo algorithm to use for convolution
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* @param workspace workspace memory which meets the requirements of \p convAlgo
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* @param filterDesc filter descriptor
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* @param[in] filterPtr pointer to device memory containing the filters
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* @param alpha convolution scale factor
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* @param inputDesc tensor descriptor describing the input
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* @param[in] inputPtr pointer to input tensor in device memory
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* @param biasDesc tensor descriptor describing the bias
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* @param[in] biasPtr pointer to bias tensor in device memory
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* @param actDesc activation descriptor
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* @param outputDesc tensor descriptor describing the output
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* @param[out] outputPtr pointer to output tensor in device memory
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*
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* Exception Guarantee: Basic
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*/
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template <class T>
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void convolve_with_bias_activation(
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const Handle& handle,
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T alpha,
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const ConvolutionDescriptor<T>& convDesc,
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const ConvolutionAlgorithm<T>& convAlgo,
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WorkspaceInstance workspace,
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const FilterDescriptor<T>& filterDesc,
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DevicePtr<const T> filterPtr,
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const TensorDescriptor<T>& inputDesc,
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DevicePtr<const T> inputPtr,
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const TensorDescriptor<T>& biasDesc,
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DevicePtr<const T> biasPtr,
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const ActivationDescriptor& actDesc,
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const TensorDescriptor<T>& outputDesc,
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DevicePtr<T> outputPtr)
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{
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CV_Assert(handle);
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T alpha2 = 0.0;
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CUDA4DNN_CHECK_CUDNN(cudnnConvolutionBiasActivationForward(
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handle.get(),
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&alpha, inputDesc.get(), inputPtr.get(),
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filterDesc.get(), filterPtr.get(),
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convDesc.get(), convAlgo.get(),
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static_cast<void*>(workspace.get()), workspace.size_in_bytes(),
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&alpha2, outputDesc.get(), outputPtr.get(),
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biasDesc.get(), biasPtr.get(),
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actDesc.get(),
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outputDesc.get(), outputPtr.get()));
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}
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template <> inline
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void convolve_with_bias_activation(
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const Handle& handle,
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half alpha,
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const ConvolutionDescriptor<half>& convDesc,
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const ConvolutionAlgorithm<half>& convAlgo,
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WorkspaceInstance workspace,
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const FilterDescriptor<half>& filterDesc,
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DevicePtr<const half> filterPtr,
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const TensorDescriptor<half>& inputDesc,
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DevicePtr<const half> inputPtr,
|
|
const TensorDescriptor<half>& biasDesc,
|
|
DevicePtr<const half> biasPtr,
|
|
const ActivationDescriptor& actDesc,
|
|
const TensorDescriptor<half>& outputDesc,
|
|
DevicePtr<half> outputPtr)
|
|
{
|
|
CV_Assert(handle);
|
|
|
|
float alpha_ = alpha, alpha2 = 0.0;
|
|
CUDA4DNN_CHECK_CUDNN(cudnnConvolutionBiasActivationForward(
|
|
handle.get(),
|
|
&alpha_, inputDesc.get(), inputPtr.get(),
|
|
filterDesc.get(), filterPtr.get(),
|
|
convDesc.get(), convAlgo.get(),
|
|
static_cast<void*>(workspace.get()), workspace.size_in_bytes(),
|
|
&alpha2, outputDesc.get(), outputPtr.get(),
|
|
biasDesc.get(), biasPtr.get(),
|
|
actDesc.get(),
|
|
outputDesc.get(), outputPtr.get()));
|
|
}
|
|
|
|
/** @brief performs convolution, bias addition, eltwise addition and activation simultaneously
|
|
*
|
|
* dstValue = act(alpha1 * conv(input) + bias + alpha2 * eltwise)
|
|
*
|
|
* @tparam T convolution element type (must be `half` or `float`)
|
|
*
|
|
* @param handle valid cuDNN Handle
|
|
* @param convDesc convolution description
|
|
* @param convAlgo algorithm to use for convolution
|
|
* @param workspace workspace memory which meets the requirements of \p convAlgo
|
|
* @param filterDesc filter descriptor
|
|
* @param[in] filterPtr pointer to device memory containing the filters
|
|
* @param alpha1 convolution scale factor
|
|
* @param inputDesc tensor descriptor describing the input
|
|
* @param[in] inputPtr pointer to input tensor in device memory
|
|
* @param biasDesc tensor descriptor describing the bias
|
|
* @param[in] biasPtr pointer to bias tensor in device memory
|
|
* @param alpha2 eltwise scale factor
|
|
* @param eltwiseDesc tensor descriptor describing the eltwise tensor
|
|
* @param[in] eltwisePtr pointer to the eltwise tensor in device memory
|
|
* @param actDesc activation descriptor
|
|
* @param outputDesc tensor descriptor describing the output
|
|
* @param[out] outputPtr pointer to output tensor in device memory
|
|
*
|
|
* Exception Guarantee: Basic
|
|
*/
|
|
template <class T>
|
|
void convolve_with_bias_eltwise_activation(
|
|
const Handle& handle,
|
|
T alpha1,
|
|
const ConvolutionDescriptor<T>& convDesc,
|
|
const ConvolutionAlgorithm<T>& convAlgo,
|
|
WorkspaceInstance workspace,
|
|
const FilterDescriptor<T>& filterDesc,
|
|
DevicePtr<const T> filterPtr,
|
|
const TensorDescriptor<T>& inputDesc,
|
|
DevicePtr<const T> inputPtr,
|
|
const TensorDescriptor<T>& biasDesc,
|
|
DevicePtr<const T> biasPtr,
|
|
T alpha2,
|
|
const TensorDescriptor<T>& eltwiseDesc,
|
|
DevicePtr<const T> eltwisePtr,
|
|
const ActivationDescriptor& actDesc,
|
|
const TensorDescriptor<T>& outputDesc,
|
|
DevicePtr<T> outputPtr)
|
|
{
|
|
CV_Assert(handle);
|
|
|
|
CUDA4DNN_CHECK_CUDNN(cudnnConvolutionBiasActivationForward(
|
|
handle.get(),
|
|
&alpha1, inputDesc.get(), inputPtr.get(),
|
|
filterDesc.get(), filterPtr.get(),
|
|
convDesc.get(), convAlgo.get(),
|
|
static_cast<void*>(workspace.get()), workspace.size_in_bytes(),
|
|
&alpha2, eltwiseDesc.get(), eltwisePtr.get(),
|
|
biasDesc.get(), biasPtr.get(),
|
|
actDesc.get(),
|
|
outputDesc.get(), outputPtr.get()));
|
|
}
|
|
|
|
template <> inline
|
|
void convolve_with_bias_eltwise_activation(
|
|
const Handle& handle,
|
|
half alpha1,
|
|
const ConvolutionDescriptor<half>& convDesc,
|
|
const ConvolutionAlgorithm<half>& convAlgo,
|
|
WorkspaceInstance workspace,
|
|
const FilterDescriptor<half>& filterDesc,
|
|
DevicePtr<const half> filterPtr,
|
|
const TensorDescriptor<half>& inputDesc,
|
|
DevicePtr<const half> inputPtr,
|
|
const TensorDescriptor<half>& biasDesc,
|
|
DevicePtr<const half> biasPtr,
|
|
half alpha2,
|
|
const TensorDescriptor<half>& eltwiseDesc,
|
|
DevicePtr<const half> eltwisePtr,
|
|
const ActivationDescriptor& actDesc,
|
|
const TensorDescriptor<half>& outputDesc,
|
|
DevicePtr<half> outputPtr)
|
|
{
|
|
CV_Assert(handle);
|
|
|
|
float alpha1_ = alpha1, alpha2_ = alpha2;
|
|
CUDA4DNN_CHECK_CUDNN(cudnnConvolutionBiasActivationForward(
|
|
handle.get(),
|
|
&alpha1_, inputDesc.get(), inputPtr.get(),
|
|
filterDesc.get(), filterPtr.get(),
|
|
convDesc.get(), convAlgo.get(),
|
|
static_cast<void*>(workspace.get()), workspace.size_in_bytes(),
|
|
&alpha2_, eltwiseDesc.get(), eltwisePtr.get(),
|
|
biasDesc.get(), biasPtr.get(),
|
|
actDesc.get(),
|
|
outputDesc.get(), outputPtr.get()));
|
|
}
|
|
|
|
}}}}} /* namespace cv::dnn::cuda4dnn::csl::cudnn */
|
|
|
|
#endif /* OPENCV_DNN_CUDA4DNN_CSL_CUDNN_CONVOLUTION_HPP */
|